Post-Silicon Validation (SoC/ASIC/FPGA)

We have well-defined methodologies that ensure design verification and validation testing effectiveness. As a part of Post-Silicon Validation, we do work on the development of a High-level Test plan and get it reviewed by design engineers, and developing the algorithms for various test flow design documents and code.


  • Preparation of test plan and interacting with the designer to get more clarity on a particular feature to be validated.
  • Tracking and reviewing the features to be validated.
  • Development of code in Embedded C, for all features to be validated.
  • Developed test cases for regression testing and stress testing.
  • Took complete ownership of IPs that Faststream is responsible for.